diff --git a/pyportal/.idea/.gitignore b/pyportal/.idea/.gitignore new file mode 100644 index 0000000..13566b8 --- /dev/null +++ b/pyportal/.idea/.gitignore @@ -0,0 +1,8 @@ +# Default ignored files +/shelf/ +/workspace.xml +# Editor-based HTTP Client requests +/httpRequests/ +# Datasource local storage ignored files +/dataSources/ +/dataSources.local.xml diff --git a/pyportal/.idea/inspectionProfiles/profiles_settings.xml b/pyportal/.idea/inspectionProfiles/profiles_settings.xml new file mode 100644 index 0000000..105ce2d --- /dev/null +++ b/pyportal/.idea/inspectionProfiles/profiles_settings.xml @@ -0,0 +1,6 @@ + + + + \ No newline at end of file diff --git a/pyportal/.idea/misc.xml b/pyportal/.idea/misc.xml new file mode 100644 index 0000000..db8786c --- /dev/null +++ b/pyportal/.idea/misc.xml @@ -0,0 +1,7 @@ + + + + + + \ No newline at end of file diff --git a/pyportal/.idea/modules.xml b/pyportal/.idea/modules.xml new file mode 100644 index 0000000..b339690 --- /dev/null +++ b/pyportal/.idea/modules.xml @@ -0,0 +1,8 @@ + + + + + + + + \ No newline at end of file diff --git a/pyportal/.idea/pyportal.iml b/pyportal/.idea/pyportal.iml new file mode 100644 index 0000000..d0876a7 --- /dev/null +++ b/pyportal/.idea/pyportal.iml @@ -0,0 +1,8 @@ + + + + + + + + \ No newline at end of file diff --git a/pyportal/.idea/vcs.xml b/pyportal/.idea/vcs.xml new file mode 100644 index 0000000..6c0b863 --- /dev/null +++ b/pyportal/.idea/vcs.xml @@ -0,0 +1,6 @@ + + + + + + \ No newline at end of file diff --git a/pyportal/code.py b/pyportal/code.py new file mode 100644 index 0000000..1e9eb2b --- /dev/null +++ b/pyportal/code.py @@ -0,0 +1,103 @@ +import time +import board +import digitalio +import supervisor + +DATA_PIN = board.SDA +CLK_PIN = board.SCL + +clock = digitalio.DigitalInOut(CLK_PIN) +data = digitalio.DigitalInOut(DATA_PIN) + +def append_to_byte(byte, value): + return (byte << 1) | (1 if value else 0) + +def get_bit_from_byte(byte, bit_pos): + return (byte >> (7-bit_pos)) & 1 + + + +def receive_data(): + data.direction = digitalio.Direction.INPUT + clock.direction = digitalio.Direction.INPUT + + last_byte = 0b0 + bit_num = 0 + + byte_arr = [] + + last_clock_state = clock.value + while True: + if clock.value != last_clock_state: + last_clock_state = not last_clock_state + bit = data.value + + print("1" if bit else "0", end='') + + last_byte = append_to_byte(last_byte, bit) + + # last_byte[bit_num] = bit + + bit_num += 1 + + if bit_num == 8: + print('') + if last_byte == 0: + break + + byte_arr.append(last_byte) + + bit_num = 0 + last_byte = 0 + return byte_arr + +# print(byte_arr) +# +# for byte in byte_arr: +# print(chr(byte), end='') + +def send_data(send_text): + data.direction = digitalio.Direction.OUTPUT + clock.direction = digitalio.Direction.OUTPUT + + + # send_text = 'This project was setup and tested using CircuitPython version 5 or higher. You will want to update your PyPortal and Libraries to match the version you are using.' + send_bytes = [0b11111111, 0b11111111] + + for char in send_text: + send_bytes.append(ord(char)) + + send_bytes.append(0b0) + + clock_state = clock.value + + num = 0 + + for byte in send_bytes: + # print(bin(byte)) + for i in range(8): + clock.value = clock_state + clock_state = not clock_state + + bit = get_bit_from_byte(byte, i) + + data.value = bit + + # print(i, end='') + print("1" if bit else "0", end='') + num += 1 + print("") + + ## Fixes another weird bug + for i in range(8): + clock.value = clock_state + clock_state = not clock_state + data.value = False + time.sleep(0.01) + +print("Started!") + +byte_arr = receive_data() + +for byte in byte_arr: + print(chr(byte), end='') \ No newline at end of file diff --git a/rpiz2/.idea/.gitignore b/rpiz2/.idea/.gitignore new file mode 100644 index 0000000..13566b8 --- /dev/null +++ b/rpiz2/.idea/.gitignore @@ -0,0 +1,8 @@ +# Default ignored files +/shelf/ +/workspace.xml +# Editor-based HTTP Client requests +/httpRequests/ +# Datasource local storage ignored files +/dataSources/ +/dataSources.local.xml diff --git a/rpiz2/.idea/inspectionProfiles/profiles_settings.xml b/rpiz2/.idea/inspectionProfiles/profiles_settings.xml new file mode 100644 index 0000000..105ce2d --- /dev/null +++ b/rpiz2/.idea/inspectionProfiles/profiles_settings.xml @@ -0,0 +1,6 @@ + + + + \ No newline at end of file diff --git a/rpiz2/.idea/misc.xml b/rpiz2/.idea/misc.xml new file mode 100644 index 0000000..db8786c --- /dev/null +++ b/rpiz2/.idea/misc.xml @@ -0,0 +1,7 @@ + + + + + + \ No newline at end of file diff --git a/rpiz2/.idea/modules.xml b/rpiz2/.idea/modules.xml new file mode 100644 index 0000000..42664f1 --- /dev/null +++ b/rpiz2/.idea/modules.xml @@ -0,0 +1,8 @@ + + + + + + + + \ No newline at end of file diff --git a/rpiz2/.idea/rpiz2.iml b/rpiz2/.idea/rpiz2.iml new file mode 100644 index 0000000..d0876a7 --- /dev/null +++ b/rpiz2/.idea/rpiz2.iml @@ -0,0 +1,8 @@ + + + + + + + + \ No newline at end of file diff --git a/rpiz2/.idea/vcs.xml b/rpiz2/.idea/vcs.xml new file mode 100644 index 0000000..6c0b863 --- /dev/null +++ b/rpiz2/.idea/vcs.xml @@ -0,0 +1,6 @@ + + + + + + \ No newline at end of file diff --git a/rpiz2/main.py b/rpiz2/main.py new file mode 100644 index 0000000..d55871d --- /dev/null +++ b/rpiz2/main.py @@ -0,0 +1,111 @@ +import time +import RPi.GPIO as GPIO +import random + + +DATA_PIN = 3 +CLK_PIN = 5 + +GPIO.setmode(GPIO.BOARD) + +def append_to_byte(byte, value): + return (byte << 1) | (1 if value else 0) + + +def get_bit_from_byte(byte, bit_pos): + return (byte >> bit_pos) & 1 + + +def send_data(send_text): + GPIO.setup(DATA_PIN, GPIO.OUT) + GPIO.setup(CLK_PIN, GPIO.OUT) + + send_bytes = [] + + for char in send_text: + send_bytes.append(ord(char)) + + send_bytes.append(0b0) + + clock_state = True + num = 0 + + for byte in send_bytes: + for i in range(8): + GPIO.output(CLK_PIN, clock_state) + clock_state = not clock_state + + bit = get_bit_from_byte(byte, i) + + GPIO.output(DATA_PIN, bit) + + print("1" if bit else "0") + time.sleep(0.1) + num += 1 + + ## Fixes another weird bug + for i in range(8): + GPIO.output(CLK_PIN, clock_state) + clock_state = not clock_state + + GPIO.output(DATA_PIN, False) + time.sleep(0.1) + + +def recieve_data(): + GPIO.setup(DATA_PIN, GPIO.IN) + GPIO.setup(CLK_PIN, GPIO.IN) + + last_byte = 0b0 + bit_num = 0 + + byte_arr = [] + + last_clock_state = GPIO.input(CLK_PIN) + + ## Due to a problem when the pyportal switches to output mode, it sends a clock signal, which needs to be ignored + + while last_clock_state == GPIO.input(CLK_PIN): + pass + last_clock_state = GPIO.input(CLK_PIN) + + while True: + clock = GPIO.input(CLK_PIN) + if clock != last_clock_state: + last_clock_state = not last_clock_state + + bit = GPIO.input(DATA_PIN) + print(bit, end='') + + last_byte = append_to_byte(last_byte, bit) + + # last_byte[bit_num] = bit + + bit_num += 1 + + if bit_num == 8: + print('') + if last_byte == 0: + break + + byte_arr.append(last_byte) + + bit_num = 0 + last_byte = 0 + + # print("### " + str(len(byte_arr))) + + return byte_arr + + +send_text = input(">") + +send_data(send_text) +# +# byte_arr = recieve_data() +# for byte in byte_arr: +# print(chr(byte), end='') + + + +print('\n\n') \ No newline at end of file