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https://github.com/Astatin3/rpiz2.git
synced 2026-06-09 00:28:05 -06:00
Attempt to make a protocol
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@@ -0,0 +1,103 @@
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import time
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import board
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import digitalio
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import supervisor
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DATA_PIN = board.SDA
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CLK_PIN = board.SCL
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clock = digitalio.DigitalInOut(CLK_PIN)
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data = digitalio.DigitalInOut(DATA_PIN)
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def append_to_byte(byte, value):
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return (byte << 1) | (1 if value else 0)
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def get_bit_from_byte(byte, bit_pos):
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return (byte >> (7-bit_pos)) & 1
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def receive_data():
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data.direction = digitalio.Direction.INPUT
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clock.direction = digitalio.Direction.INPUT
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last_byte = 0b0
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bit_num = 0
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byte_arr = []
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last_clock_state = clock.value
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while True:
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if clock.value != last_clock_state:
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last_clock_state = not last_clock_state
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bit = data.value
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print("1" if bit else "0", end='')
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last_byte = append_to_byte(last_byte, bit)
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# last_byte[bit_num] = bit
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bit_num += 1
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if bit_num == 8:
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print('')
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if last_byte == 0:
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break
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byte_arr.append(last_byte)
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bit_num = 0
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last_byte = 0
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return byte_arr
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# print(byte_arr)
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#
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# for byte in byte_arr:
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# print(chr(byte), end='')
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def send_data(send_text):
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data.direction = digitalio.Direction.OUTPUT
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clock.direction = digitalio.Direction.OUTPUT
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# send_text = 'This project was setup and tested using CircuitPython version 5 or higher. You will want to update your PyPortal and Libraries to match the version you are using.'
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send_bytes = [0b11111111, 0b11111111]
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for char in send_text:
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send_bytes.append(ord(char))
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send_bytes.append(0b0)
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clock_state = clock.value
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num = 0
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for byte in send_bytes:
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# print(bin(byte))
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for i in range(8):
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clock.value = clock_state
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clock_state = not clock_state
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bit = get_bit_from_byte(byte, i)
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data.value = bit
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# print(i, end='')
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print("1" if bit else "0", end='')
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num += 1
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print("")
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## Fixes another weird bug
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for i in range(8):
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clock.value = clock_state
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clock_state = not clock_state
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data.value = False
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time.sleep(0.01)
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print("Started!")
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byte_arr = receive_data()
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for byte in byte_arr:
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print(chr(byte), end='')
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